About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Location: Santa Clara, CA

Salary Range: $140k-200k

Job Summary

EdgeQ is looking to add experienced members to the product management team to develop and manage innovative semiconductor products for 5G/6G wireless infrastructure for Terrestrial and Non-Terrestrial (NTN) Markets. The key responsibility is to identify edge AI use cases and requirements (ex: latency) for different physical AI scenarios. The role will also be responsible for identifying market demands and new trends from customer engagement, instituting best business practices for the company, developing revenue-generating customer funnel, validating business cases through complex analyses of the ecosystem, technology, and competitive landscape; building strategic partnerships, and driving the complete product life cycle from cradle to grave.

Responsibilities

• Build strategic partnerships with Carrier Operators (Terrestrial and Satellite) and OEMs/ODMs and own the account from pre-sales to post sales
• Business owner for strategic customer accounts from cradle to grave -- Own pricing, customer success, roadmap features, and alignment with engineering
• Define, own and implement roadmaps of product features with in-depth knowledge of customer needs and engineering resources. Work and drive alignment with the engineering team on the planning and execution vis-a-vis corporate objectives.
• Define the next generation product for EdgeQ’s growing business -- Analyze market demands and build business cases along with technology roadmap for Physical AI use cases.
• Define, implement, and institute corporate wide business processes congruent with product life cycles and customer life cycles
• Inbound/Outbound support of customers and EdgeQ sales, apps engineering, and product engineering
• Monitor and analyze market trends, competition, and customer feedback to identify opportunities for product improvement and innovation.

Requirements

• A Master's or a PhD degree in engineering or related field, with an MBA preferred.
• Deep knowledge of Modem technology, including cellular network standards (5G/LTE and 6G)
• Knowledge of Edge AI and Physical AI uses cases and requirements is a solid plus.
• Solid understanding of Networking Stack and Protocols will be viewed as added advantage.
• ~5-10 years of experience in product management, with at least 2-3 years of experience in the AI and/or Telecommunication industry.
• Experience in a fast-paced startup environment is highly desired.
• Proven experience in new product introduction and scaling business.
• Track record of successful product launches and revenue growth
• Ability to manage cross-functional teams and collaborate with engineering teams in an agile environment.

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 3–15 Years

Location: Bangalore, India

Job Description

EdgeQ is looking for talented RTL Design Engineers across experience levels to join our design team developing high-performance, power-efficient semiconductor solutions for 5G/6G, edge computing, and networking applications. We are looking for engineers who are passionate about building high-performance and power-efficient silicon and can take ownership of RTL development from specification through implementation and tape out.

Responsibilities

• Design and develop synthesizable RTL using Verilog/System Verilog based on architectural and microarchitectural specifications.
• Work on microarchitecture, RTL coding, lint, CDC, synthesis, timing, and design-quality closure.
• Optimize designs for power, performance, and area (PPA).
• Debug RTL and simulation issues and work closely with verification, architecture, physical design, DFT, and firmware teams.
• Participate in IP/subsystem integration, design reviews, and tape out activities.
• Develop reusable and high-quality RTL following established design methodologies.

Required Skills

• Strong fundamentals in digital design and computer architecture.
• Hands-on experience with Verilog/System Verilog RTL design.
• Experience with ASIC/SoC development and related RTL design flows.
• Strong debugging and problem-solving skills.

Good to Have

Experience with any of the following - 5G/6G, RISC-V, O-RAN/eCPRI, JESD204, Ethernet, PCIe, UCIe, SerDes, DSP/data-path design, low-power design, or other high-speed interfaces.

Education

B.Tech/M.Tech/M.S./PhD in Electrical/Electronics Engineering, VLSI, Computer Engineering, or a related field.

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 3–15 Years

Location: Bangalore, India

Job Description

EdgeQ is looking for talented Design Verification Engineers across experience levels to join our verification team working on complex semiconductor designs for 5G/6G, edge computing, and networking applications. We are looking for engineers who are passionate about building robust verification environments and ensuring high-quality silicon through comprehensive IP, SoC, and post-silicon verification. The role covers verification at IP, subsystem, SoC, and post-silicon levels.

Responsibilities

• Develop and execute verification strategies for digital IPs, subsystems, and complete SoCs.
• Develop testbenches, test scenarios, sequences, checkers, scoreboards, assertions, and functional coverage.
• Work with System Verilog and UVM to build scalable and reusable verification environments.
• Verify complex data paths, control logic, memories, interfaces, and system-level functionality.
• Perform block, IP, subsystem, and SoC-level verification including integration and system-level scenarios.
• Debug simulation, formal, emulation, FPGA, and silicon issues and work closely with design and architecture teams.
• Drive functional and code coverage closure and identify verification gaps.
• Develop automation and verification infrastructure to improve regression, debug, and overall verification efficiency.
• Support pre-silicon verification, silicon bring-up, post-silicon validation, and debug activities.

Required Skills

• Strong fundamentals in digital design and computer architecture.
• Hands-on experience with Verilog/System Verilog and verification methodologies.
• Experience with System Verilog/UVM-based verification environments.
• Good understanding of constrained-random verification, assertions, functional coverage, and regression.
• Strong debugging and problem-solving skills.
• Experience with ASIC/SoC verification flows.
• Verify low-power designs and power-management features using UPF, including power domains, isolation, retention, power states, and power sequencing.

Good to Have

Experience with any of the following - 5G/6G, RISC-V, O-RAN/eCPRI, JESD204, Ethernet, PCIe/CXL, UCIe, SerDes, Network-on-Chip (NoC), DSP/data path verification, low-power verification, formal verification, emulation/FPGA validation, or post-silicon debug.

Education

B.Tech/M.Tech/M.S. in Electrical/Electronics Engineering, VLSI, Computer Engineering, or a related field.

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 4–12 Years

Location: Bangalore, India

Job Description

EdgeQ is looking for talented L2/L3 Engineers working on 5G NR, FR1 and FR2/mmWave, NTN (Non-Terrestrial Networks) technologies.

Responsibilities

• 5G Protocol Stack (MAC, RLC, PDCP, RRC)
• NTN and FR2/mmWave technologies
• C/C++ and Linux development
• Telecom software, performance optimization, and system debugging
• 3GPP standards and wireless networking

Education

B.Tech/M.Tech/M.S. in Electrical/Electronics Engineering, VLSI, Computer Engineering, or a related field.

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 5+ Years

Location: Santa Clara, US

Responsibilities

• Design the micro-architecture of ML accelerator sub-blocks based on system-level architecture specifications
• Implement power and area efficient sub-blocks with SystemVerilog, e.g. MAC arrays, vector engines, activation/normalization units, data-movement and memory controllers
• Write micro-architecture specifications and design documents
• Develop control and datapath RTL, run Lint/CDC/LEC, and integrate sub-blocks into the accelerator subsystem
• Perform bit-exact verification against C/C++/Python reference models with the architecture and software teams
• Optimize the HW to meet area, timing, and power targets; perform synthesis and power analysis
• Implement low-power logic (clock gating, power domains, memory power management)
• Work with the Design Verification team on block-level and top-level functional/gate-level verification and coverage, including power-aware debug
• Support physical design for timing closure and post-silicon bring-up, debug, and performance measurement
• Guide and review the work of junior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 5+ years of ASIC design experience
• Professional knowledge and experience in System Verilog RTL design
• Experience designing ML accelerator or compute building blocks such as MAC/systolic arrays, vector/SIMD units, activation/pooling/normalization units, or DMA engines
• Solid understanding of neural network operations (convolution, GEMM, attention, softmax) and their mapping to hardware
• Knowledge of numeric formats and quantization (INT8/INT4, FP16/BF16/FP8) and floating-point/fixed-point arithmetic design
• Strong skills in pipelining, data reuse, and resource sharing for area and power optimization
• Hands-on experience in front-end chip development: Lint, CDC, LEC, synthesis, timing constraints, and low-power checks (UPF)
• Experience with multiple clock domains and asynchronous interfaces
• Experience writing micro-architecture specifications and converting them to design
• Knowledge of on-chip buses (AXI/AHB/APB), SRAM interfaces, memory banking, and scratchpad design
• Ability to communicate effectively across all internal groups

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 10+ Years

Location: Santa Clara, US

Responsibilities

• Define the overall HW architecture of the ML accelerator, including compute engines, memory hierarchy, interconnect, and control
• Translate target workloads and system requirements into architecture and micro-architecture specifications with clear PPA (TOPS/W, TOPS/mm²) targets
• Perform workload analysis and architecture exploration (roofline, utilization, bandwidth, latency) to size compute and memory resources
• Drive HW/SW co-design with the compiler, runtime, and firmware teams, including ISA and programming model definition
• Architect power and area efficient MAC arrays, vector units, activation/normalization units, and data-movement engines
• Lead block-level and subsystem-level RTL design teams; review micro-architecture, RTL, and verification plans
• Own PPA closure of the accelerator together with physical design, ensuring timing, area, and power goals are met
• Collaborate with modem architecture, SoC integration, verification, DFT, and physical design teams
• Support post-silicon bring-up, debug, and performance benchmarking
• Mentor staff and junior engineers and set design methodology and quality standards

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 10+ years of ASIC design experience
• Proven track record of architecting and taping out ML/AI accelerators, GPUs, DSPs, or high-performance compute engines
• Deep understanding of ML/AI accelerator architecture: matrix/tensor engines, systolic arrays, dataflow (weight/output/row stationary), and vector/SIMD units
• Expert in power, performance and area (PPA) trade-offs: roofline analysis, data reuse, clock and power gating, DVFS, and low-power design (UPF)
• Expert in SystemVerilog RTL and front-end flows (Lint, CDC/RDC, LEC, synthesis, STA constraints, power analysis)
• Experience with RISC-V or custom ISA extensions for ML, and HW/SW co-design with ML compilers and runtimes (e.g. TVM, MLIR, ONNX)
• Strong knowledge of neural network workloads (CNN, RNN, Transformer/attention, LLM inference) and their compute, memory, and bandwidth characteristics
• Experience with numeric formats and quantization (INT8/INT4, FP16/BF16/FP8, block floating point) and sparsity/compression techniques
• Expert in on-chip memory hierarchy design: SRAM banking, scratchpads, DMA engines, prefetch, and DDR/LPDDR bandwidth optimization
• Familiarity with ML workloads for wireless (AI-native PHY, channel estimation, beam management) is a plus
• Excellent written and verbal communication; able to lead cross-functional technical discussions and mentor engineers

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 1-5 Years, or new Graduate

Location: Santa Clara, US

Responsibilities

• Design and implement digital logic blocks for ML accelerator subsystems using SystemVerilog
• Develop RTL for control logic, arithmetic datapaths, register interfaces, FIFOs, and bus/DMA interfaces according to specifications
• Work with the design and verification teams to simulate and debug blocks, and close functional coverage
• Run front-end checks (Lint, CDC, synthesis) and help optimize designs for area, timing, and power
• Help build C/Python reference models and test vectors with the architecture and software teams
• Develop scripts and tools to automate design and verification flows
• Support FPGA prototyping, block integration, and post-silicon validation and benchmarking
• Learn ML accelerator architecture and workload mapping under the mentorship of senior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field, with 1–5 years of experience; new graduates (MS/PhD) are welcome
• Excellent knowledge of digital logic design: combinational/sequential logic, FSMs, pipelining, timing (setup/hold), and arithmetic circuits
• Excellent knowledge of computer architecture and microprocessors: instruction pipelines, hazards, caches, memory hierarchy, and interrupts
• Hands-on RTL design experience in Verilog/SystemVerilog through projects, internships, or industry work
• Coursework or project experience in machine learning and neural network fundamentals
• Experience designing a processor (e.g. RISC-V core), systolic array, or ML accelerator in coursework, research, or FPGA projects is a strong plus
• Familiarity with simulation and synthesis tools (e.g. VCS/Xcelium, Verdi, Design Compiler/Genus, Vivado/Quartus)
• Understanding of integer/floating-point arithmetic, clock domain crossing, and low-power design concepts is a plus
• Programming/scripting skills in C/C++ and Python; familiarity with PyTorch or TensorFlow is a plus
• Strong problem-solving skills, eagerness to learn, and good communication and teamwork skills

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 5+ Years

Location: Santa Clara, US

Responsibilities

• Design the micro-architecture of modem sub-blocks based on system-level architecture specifications
• Implement power and area efficient sub-blocks with SystemVerilog, e.g. channel estimation, MIMO equalizer, FFT, LDPC/Polar decoder, and NTN Doppler/timing compensation
• Write micro-architecture specifications and design documents
• Develop control and datapath RTL, run Lint/CDC/LEC, and integrate sub-blocks into subsystems
• Perform bit-exact verification against C/MATLAB reference models with the algorithm team
• Optimize the HW to meet area, timing, and power targets; perform synthesis and power analysis
• Implement low-power logic (clock gating, power domains, memory power management)
• Work with the Design Verification team on block-level and top-level functional/gate-level verification and coverage, including power-aware debug
• Support physical design for timing closure and post-silicon bring-up and debug
• Guide and review the work of junior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 5+ years of ASIC design experience
• Professional knowledge and experience in SystemVerilog RTL design
• Professional knowledge of digital signal processing and wireless communication; familiarity with 4G LTE / 5G NR physical layer
• Experience designing DSP datapaths such as FFT, filters, correlators, MMSE/ML equalizers, matrix operations, or LDPC/Polar encoders/decoders
• Strong skills in fixed-point arithmetic, pipelining, and resource sharing for area and power optimization
• Hands-on experience in front-end chip development: Lint, CDC, LEC, synthesis, timing constraints, and low-power checks (UPF)
• Experience with multiple clock domains and asynchronous interfaces
• Experience writing micro-architecture specifications and converting them to design
• Knowledge of on-chip buses (AXI/AHB/APB), SRAM interfaces, and memory banking
• Knowledge of 5G NTN (satellite) features such as Doppler and timing compensation is a plus
• Ability to communicate effectively across all internal groups

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 10+ Years

Location: Santa Clara, US

Responsibilities

• Define the overall HW architecture of major 4G/5G modem blocks for gNB and UE, terrestrial and NTN
• Translate 3GPP, system, and algorithm requirements into architecture and micro-architecture specifications with clear PPA targets
• Drive HW/SW partitioning between fixed-function HW accelerators, vector processing engines, and CPUs/firmware
• Perform architecture exploration and modeling (throughput, latency, memory bandwidth, timeline budgets) to size compute and memory resources
• Architect power and area efficient datapaths, memory subsystems, and control for channel estimation, MIMO equalization, channel coding/decoding, and NTN compensation
• Lead block-level and subsystem-level RTL design teams; review micro-architecture, RTL, and verification plans
• Own PPA closure of major blocks together with physical design, ensuring timing, area, and power goals are met
• Collaborate with algorithm, firmware/software, verification, DFT, and physical design teams throughout the chip development cycle
• Support post-silicon bring-up, debug, and performance characterization
• Mentor staff and junior engineers and set design methodology and quality standards

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 10+ years of ASIC design experience
• Proven track record of architecting and taping out major baseband blocks or subsystems in high-volume wireless SoCs
• Hands-on architecture experience with key PHY blocks such as FFT/IFFT, channel estimation, MIMO detection (MMSE/ML), beamforming, LDPC/Polar/Turbo codecs, rate matching, HARQ, and digital front-end
• Experience with vector/DSP processors or RISC-V-based programmable engines and HW/SW partitioning of PHY processing
• Experience with both gNB (base station) or UE (device) baseband requirements, including multi-cell/multi-user scaling, throughput, and latency budgets
• Experience with multiple clock domains, asynchronous interfaces, on-chip interconnects (AXI/NoC), and SRAM/DDR memory subsystems
• Expert in power, performance and area (PPA) trade-offs: fixed-point analysis, memory partitioning/banking, clock and power gating, DVFS, and low-power design (UPF)
• Expert in SystemVerilog RTL and front-end flows (Lint, CDC/RDC, LEC, synthesis, STA constraints, power analysis)
• Deep knowledge of digital signal processing and wireless communication; expert understanding of 4G LTE / 5G NR physical layer (3GPP Rel-15 onward)
• Knowledge of 5G NTN (satellite) requirements such as large Doppler/timing pre-compensation, long round-trip delay, and HARQ/timing-advance handling is a strong plus
• Excellent written and verbal communication; able to lead cross-functional technical discussions and mentor engineers

About EdgeQ

EdgeQ is a leading innovator developing the industry’s first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 1-5 Years, or new Graduate

Location: Santa Clara, US

Responsibilities

• Design and implement digital logic blocks for 4G/5G modem subsystems using SystemVerilog
• Develop RTL for control logic, DSP datapaths, register interfaces, FIFOs, and bus interfaces according to specifications
• Work with the design and verification teams to simulate and debug blocks, and close functional coverage
• Run front-end checks (Lint, CDC, synthesis) and help optimize designs for area, timing, and power
• Help build MATLAB/C/Python reference models and test vectors with the algorithm team
• Develop scripts and tools to automate design and verification flows
• Support FPGA prototyping, block integration, and post-silicon validation
• Learn 4G/5G physical layer (terrestrial and NTN) and modem architecture under the mentorship of senior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field, with 1–5 years of experience; new graduates (MS/PhD) are welcome
• Excellent knowledge of digital logic design: combinational/sequential logic, FSMs, pipelining, timing (setup/hold), and arithmetic circuits
• Excellent knowledge of computer architecture and microprocessors: instruction pipelines, hazards, caches, memory hierarchy, and interrupts
• Hands-on RTL design experience in Verilog/SystemVerilog through projects, internships, or industry work
• Coursework or project experience in digital signal processing and wireless communication (OFDM, MIMO, channel coding)
• Experience designing a processor (e.g. RISC-V core) or DSP block in coursework, research, or FPGA projects is a strong plus
• Familiarity with simulation and synthesis tools (e.g. VCS/Xcelium, Verdi, Design Compiler/Genus, Vivado/Quartus)
• Understanding of fixed-point arithmetic, clock domain crossing, and low-power design concepts is a plus
• Strong problem-solving skills, eagerness to learn, and good communication and teamwork skills

About the Role

We are looking for a Senior QA Engineer with deep expertise in platform software validation to join EdgeQ's engineering team in Bangalore. Background in semiconductors, SoC bring up, or embedded hardware system background is mandatory. Wireless background in 4G/5G is ideally preferred.

You will own test strategy, automation infrastructure, and quality processes for embedded Linux-based platforms, including networking and radio access network (RAN) stack components. You will work closely with kernel, firmware, and software engineers to define test coverage, build robust automation pipelines, and drive quality across the full software stack.

Responsibilities

• Design, develop, and maintain automated test frameworks for embedded Linux platform software including kernel, drivers, and system-level components
• Build and manage test automation using the Robot Framework and Python, covering functional, regression, integration, and stress testing
• Deploy and administer LAVA (Linaro Automated Validation Architecture) test infrastructure for continuous hardware-in-the-loop testing across target boards
• Develop test plans and test cases for network stack validation including L2/L3 protocols, RAN components (MAC, RLC, PDCP), and inter-process communication
• Collaborate with development teams to integrate automated tests into CI/CD pipelines using Git-based workflows
• Triage and root-cause test failures, distinguishing infrastructure issues from genuine software defects
• Define and track quality metrics, test coverage reports, and release readiness criteria
• Review and contribute to system architecture and design documents from a testability perspective
• Mentor junior QA engineers and establish best practices for test automation and documentation
• Participate in agile sprints, contributing QA estimates, test plans, and risk assessments

Required Qualifications

• 5–10 years of experience in software QA with a focus on platform, embedded, or systems-level testing
• Strong hands-on experience with embedded Linux — kernel configuration, device drivers, system bring-up, and debugging
• Proficiency in Python for test automation, tooling, and infrastructure scripting
• Experience with Robot Framework for test case development, keyword libraries, and test suite management
• Hands-on experience with LAVA for automated board farm testing and remote device management
• Solid understanding of network stack protocols (TCP/IP, UDP, Ethernet) and experience testing network interfaces or communication stacks
• Proficient with Git for version control, branching strategies, and code review workflows
• Experience writing test plans, test specifications, and bug reports with high clarity and technical detail
• Strong debugging skills using tools such as GDB, strace, ftrace, perf, Wireshark, or serial console
• Bachelor's or Master's degree in Computer Science, Electronics Engineering, or a related technical discipline

Preferred Qualifications

• Experience with RAN stack components (MAC, RLC, PDCP, PHY layer interfaces) or telecom platform testing
• Familiarity with real-time Linux (PREEMPT_RT) and its testing considerations
• Experience with UIO (Userspace I/O), shared memory IPC, or inter-process communication testing
• Knowledge of JTAG debugging, OpenOCD, or hardware bring-up workflows
• Familiarity with CI/CD systems such as Jenkins, GitLab CI, or GitHub Actions
• Experience with cross-compilation environments and ARM64 target platforms
• Understanding of performance testing and profiling methodologies for embedded systems
• Contributions to open-source projects or internal tooling infrastructure

Work Environment

• Full-time, on-site position based at our Bangalore office
• Collaborative lab environment with access to hardware boards, test infrastructure, and engineering tools
• Close coordination with global engineering teams across time zones

At EdgeQ, our vision is a hyper-connected world achieved through implementing 5G in a format that is accessible, consumable, and intuitive. As a leading innovator, EdgeQ is the creator of the industry’s first 5G Base-Station-on-a-Chip. Led by seasoned executives who have delivered industry-transforming technologies (4G/5G, WiFi, Wimax, Artificial Intelligence, Cloud Servers) for the last few decades, EdgeQ is inventing a new paradigm within the wireless infrastructure industry.

As an engineer of the Platform Software team, you will help build a dynamic platform for the next generation 5G SoC at EdgeQ. You will be in a fast paced environment and challenged creatively as you interact with internal and external customers. Must be able to own, implement and optimize data plane stacks.

Role Summary and Responsibilities

• Identifying bottlenecks in networking and communication protocols
• Developed DPDK PMD and DPDK fast path
• Putting together DPDK on an ARMv8 embedded system
• Troubleshooting and optimizing data path
• Architect the next generation 5G base station on a chip’s data path

Job Requirements

• Strong programming experience in c/c++
• In-depth knowledge in packet forward path in layer 2 and layer 3
• Hands on experience with DPDK fastpath
• 5G RAN architecture knowledge preferred but not required
• Have good knowledge and experience working in Linux environment
• 10 years experience with DPDK preferred

Accessibility

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

Role Summary and Responsibilities

• Design and develop high quality functional firmware
• Translate product requirements to FW functional requirements
• Write detailed FW architecture specification covering functional, performance and KPI aspects
• Write detailed FW architecture specification covering functional, performance and KPI aspects
• Develop high level design, low-level design specification
• Design FW system to handle critical timing/synchronization to meet real-time needs of wireless protocols
• Closely work with HW architects and system engineers to design HW-SW functional split and interfaces
• Active part in Customer solution design
• Functional troubleshooting at product level both in the lab and field
• Perform effective SW/FW configuration management and release management
• Support field performance activities and radio conformance tests

Job Requirements

• Strong knowledge of any of the wireless technologies (4G, 5G, WLAN technologies (802.11a/b/g/n/ac/ax))
• Strong background in Wireless communication and signal processing
• Deep understanding of embedded software engineering principles, and core computer science fundamentals
• RTOS, C and C++, compilers, build and source code control tools;
• Very strong coding & debugging skills in C is must
• Proficiency debugging embedded software systems
• Education & experience:B.Tech Degree in Electronics & Communication, Telecom System Engineering or Computer Science. MS/M.Tech Degree highly desirable
• 2-12 years’ experience Wireless PHY, PHY control Firmware design and development

Accessibility

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

EdgeQ is a leading innovator creating the industry’s first 5G Base-Station-on-a-Chip. We have assembled a formidable team of distinguished engineers, domain experts, and top graduates from the world’s most selective universities to unlock what has traditionally been a proprietary, expensive and complex solution. It takes great innovative minds to unlock the potential of 5G into transformative products. This is where you come in to be one of the key drivers of this transformation.

Role Summary and Responsibilities

• You will be part of the software team delivering high-performance software for a novel reference platform on an aggressive timeline.
• You will be part of a team delivering a custom high-performance PHY and RF modules on an aggressive timeline.
• You will be part of a team that handles design and development of complex low-level SW and FW to enable the development of air interface solutions with focus on L1, Phy and RF functions based on customer driven requirements.
• Responsibilities include developing signal processing features and algorithms using cutting edge SoC, DSP, Baseband, RF transceiver and WTR engine technologies.
• You will be contributing to the latest ideas and developments in wireless communication enabling IoT, Vehicular communication(V2X), Augmented Reality, Automated Factories of the future. Are you ready to take the plunge?

Job Requirements

• Strong background in Wireless communication and signal processing
• Very strong coding & debugging skills in C is must
• Knowledge of any of the wireless technologies (4G, 5G, WLAN technologies (802.11a/b/g/n/ac/ax)) is a plus.
• Deep understanding of embedded software engineering principles, and core computer science fundamentals
• Knowledge of RTOS, compilers, build and source code control tools will be a plus
• Education & experience:B.Tech Degree in Electronics & Communication, Telecom System Engineering or Computer Science. MS/M.Tech Degree highly desirable

Accessibility

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

At EdgeQ, our vision is a hyper-connected world achieved through implementing 5G in a format that is accessible, consumable, and intuitive. As a leading innovator, EdgeQ is the creator of the industry’s first 5G Base-Station-on-a-Chip. Led by seasoned executives who have delivered industry-transforming technologies (4G/5G, WiFi, Wimax, Artificial Intelligence, Cloud Servers) for the last few decades, EdgeQ is inventing a new paradigm within the wireless infrastructure industry.

As an engineer of the Platform Software team, you will help build a dynamic platform for the next generation 5G SoC at EdgeQ. You will be in a fast paced environment and challenged creatively as you interact with internal and external customers. Must be able to own, implement and optimize Linux kernel device drivers, RTOS firmware and Linux application stacks.

Role Responsibilities

• Develop and design Linux kernel device drivers
• Optimize driver and kernel using common Linux tools
• Troubleshoot kernel OS and device driver bugs
• Architect next generation 5G platform software
• Interface with internal and external customers to resolve critical issues

Requirements

• Have the professional knowledge/experience on C & assembly language
• Linux environment development experience
• Understanding of SPI, I2C, UART, PCIe, Ethernet device drivers
• Knowledge of Linux networking stack

Accessibility

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.