5G ASIC Designer
Role Summary and Responsibilities
- RTL Logic Design experience of multi-million gate ASICs.
- Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
- Work with Design Verification team on top-level or block level functional/gate level verification and code coverage, including power aware debug.
- Top/Block level RTL (Verilog or System Verilog) design, integration.
- Implementation of Low power logic, targeting power, performance, area, and timing goals
- Work on Linting, CDC, LEC and preferably Low Power check tools to implement design and check design quality
- Experience with multiple clock domains and asynchronous interfaces.
- Experience writing specifications and converting them to design.
- Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
- Ability to communicate effectively across all internal groups.
- Familiarity with software and operating concepts is a plus.
- Familiarity with scripting languages like Python is a plus.
- Experience of 10+ years is a must