Careers

Open Positions

Operations

Data Plane Software Developer

Bangalore, India & Santa Clara, US

Operations

L2/L3 Infrastructure Software Developer

Bangalore, India & Santa Clara, US

Operations

L3 Sr Technical/Principal Engineer – 5G

Bangalore, India

Operations

L2 Technical Engineer – 5G

Bangalore, India & Santa Clara, US

Operations

L3 Technical Engineer – 5G

Bangalore, India

Operations

Design Verification (Sub-system &/or SoC)

Bangalore, India

Operations

Design Engineer / Lead

Santa Clara, California or Bangalore, India

Operations

Physical Design Engineer / STA Lead

Bangalore, India

Operations

5G ASIC Designer

Santa Clara or San Diego, California

Operations

Firmware Engineering

Santa Clara, California or Bangalore, India

Operations

5G PHY Control Firmware​

Santa Clara, California or Bangalore, India

Operations

Digital Signal Processing (Micro-Kernel) Engineer

Santa Clara or San Diego, California

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Data Plane Software Developer

Bangalore, India & Santa Clara, US

Role Summary and Responsibilities

  • In-depth knowledge in packet forward path in layer 2 and layer 3
  • Experience in identifying bottlenecks in networking and communication patterns
  • Experience in optimization data plane software such as dpdk for an embedded system
  • Develop high level design, low-level design specification

Job Requirements

  • Strong programming experience in c/c++
  • Linux system, kernel, device driver programming experience
  • Hands on experience with vpp preferred
  • 5G RAN architecture knowledge preferred

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

L2 Sr Technical/Principal Engineer – 5G

L2/L3 Infrastructure Software Developer

Bangalore, India & Santa Clara, US

Role Summary and Responsibilities

  • Strong programming experience in c/c++
  • Linux system, kernel, device driver programming experience
  • Experience with VM on ARM cpus preferred

Job Requirements

  • Good understanding and hands-on experience in Linux kernel memory subsystem
  • Experience of development multi-core, multi-threaded application for Linux system
  • Good understanding of l2/l3 networking protocol
  • Linux socket programming experience
  • Hands on experience on Marvell SoC

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

L2 Sr Technical/Principal Engineer – 5G

L3 Sr Technical/Principal Engineer – 5G

Bangalore, India

Role Summary and Responsibilities

Your role will include digital radio design activities such as:

  • Design and develop high quality functional software
  • Translate product requirements to SW functional requirements
  • Write detailed SW architecture specification covering functional, performance and KPI aspects
  • Develop high level design, low-level design specification
  • Design SW system to handle critical timing/synchronization to meet real-time needs of a 4G/5G Radio
  • Design and develop SW component tests and Radio product tests
  • Closely work with radio designers and design HW-SW interfaces
  • Active part in Customer solution design
  • Close cooperation with CPU, FPGA and RF circuits vendors
  • Design a lab set-up for Digital radio SW validation
  • Functional troubleshooting at product level both in the lab and field
  • Perform effective SW configuration management and SW release managment
  • Support field performance activities and radio conformance tests

Job Requirements

  • In-depth knowledge of radio development for mobile networks, especially on 3GPP LTE and NR
  • Participate in customer calls and translate the customer requirements into product and SW requirements
  • Experience in 5G NR/LTE and LTE Advanced RAN product development is a must
  • Excellent experience in L3 layers especially in Radio Resource Management, RRC, eNodeBApp/gNodeBApp and Radio
    protocol stack is must
  • Should be handson C coder. (Principal role] Excellent C coding abilities. (Sr. Technical role)
  • Experience of 8+ years in LTE RAN product development required (Principal role)
  • Experience of 6+ years in LTE RAN product development required (Sr. Technical role)
  • In depth hands-on experience in real-time system design specifically in 3GPP LTE and NR
  • Excellent Design, Debug and Architecture skills a must
  • Able to lead a team of 12-15 members on technical aspects (Principal role)
  • Able to lead a team of 6-8 members on technical aspects (Sr. Technical role)
  • B.Tech Degree in Electronics & Communication, Telecom System Engineering or Computer Science. MS/M.Tech Degree highly desirable
  • At least 10+ years’ experience in mobile telecommunication industry preferably in RAN product development (Principal role)
  • At least 8+ years’ experience in mobile telecommunication industry preferably in RAN product development (Sr. Technical role)
  • Proven track record on RAN product development and customer delivery
  • Ability to quickly grasp and adapt to new technologies and concepts
  • Should be a great team player who can work across functional teams and drive the team technically with sound judgement
  • Excellent presentation skills for a variety of audiences including executives, partners, and customers
  • Excellent understanding of SW development and Architecture principles
  • Excellent verbal and written communication skills
  • Excellent inter-personal skills

Accessibility

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

L3 Sr Technical/Principal Engineer – 5G

L2 Technical Engineer-5G

Bangalore, India & Santa Clara, US

Role Summary and Responsibilities

Your role will include digital radio design activities such as:

  • Design and develop high quality functional software
  • Develop high level design, low-level design specification
  • Design SW system to handle critical timing/synchronization to meet real-time needs of a 4G/5G Radio
  • Design and develop SW component tests and Radio product tests
  • Closely work with radio designers and design HW-SW interfaces
  • Close cooperation with CPU, FPGA and RF circuits vendors
  • Functional troubleshooting at product level both in the lab and field
  • Perform effective SW configuration management and SW release managment
  • Support field performance activities and radio conformance tests

Job Requirements

  • In-depth knowledge of radio development for mobile networks, especially on 3GPP LTE and NR
  • 2-3 years Experience in 4G LTE and LTE Advanced RAN product development is a must >
  • Excellent experience in L2 layer.
  • Candidate should have the ability to extract relevant information from 3GPP specs for the work at hand.
  • Should be having excellent C coding skills.
  • Should be able to devise Unit Test and Integration Test cases for the feature at hand.
  • Any prior experience on 5G Layer2 will be a plus.
  • Shall be great team player
  • Excellent understanding of SW development and Architecture principles
  • Excellent inter-personal skills
  • Excellent verbal and written communication skills
  • Ability to quickly grasp and adapt to new technologies and concepts.
  • B.Tech Degree in Electronics & Communication, Telecom System Engineering or Computer Science. MS/M.Tech Degree highly desirable
  • At least 2+ years’ experience in mobile telecommunication industry preferably in RAN product development
 

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

L2 Technical Engineer-5G

L3 Technical Engineer – 5G

Bangalore, India

Role Summary and Responsibilities

Your role will include digital radio design activities such as:

  • Design and develop high quality functional software
  • Develop high level design, low-level design specification
  • Design SW system to handle critical timing/synchronization to meet real-time needs of a 4G/5G Radio
  • Design and develop SW component tests and Radio product tests
  • Closely work with radio designers and design HW-SW interfaces
  • Close cooperation with CPU, FPGA and RF circuits vendors
  • Functional troubleshooting at product level both in the lab and field
  • Perform effective SW configuration management and SW release managment
  • Support field performance activities and radio conformance tests

Job Requirements

  • In-depth knowledge of radio development for mobile networks, especially on 3GPP LTE and NR
  • 2+ years Experience in 4G LTE and LTE Advanced RAN product development
  • Excellent experience in LTE L3 layers especially in Radio Resource Management and eNodeBApp
  • Experience in 5G NR in L3 layers – Radio Resource Management, RRC and gNodeBApp – is a plus
  • Should be excellent in C coding
  • Should be able to interpret 3GPP specifications
  • In-depth knowledge of radio development for mobile networks, especially on 3GPP LTE and NR
  • 2+ years Experience in 4G LTE and LTE Advanced RAN product development
  • Excellent experience in LTE L3 layers especially in Radio Resource Management and eNodeBApp
  • Experience in 5G NR in L3 layers – Radio Resource Management, RRC and gNodeBApp – is a plus
  • Should be excellent in C coding
  • Should be able to interpret 3GPP specifications

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

L3 Technical Engineer – 5G

Design Verification (Sub-system &/or SoC)

Bangalore, India

Job Requirements [Sub-system DV]:

  • Strong hands-on experience in C based HW (IP sub-system) verification
  • Required to have familiarity and environment development experience which is UVM based (Sequences, Scoreboard)
  • Must have strong knowledge on Bus protocols (AXI/AHB/APB)
  • Experience with signal processing DV background is a plus
  • Nice to have Network on Chip/ Interconnect debugging experience
  • Functional Coverage
  • Coverage analysis and closure

Job Requirements [SoC DV]:

  • Hands-on SoC verification environment development and integration expertise
  • Strong understanding and development experience with C based verification flows, and tests, which involves multiple processor cores
  • Must have strong knowledge on Bus protocols (AXI/AHB/APB)
  • Should be proficient in Verilog/ System – Verilog
  • Candidates with experience integrating Verification IPs (VIPs) for protocols such as DDR, PCIe, Ethernet, USB will be preferred
  • ARM / RISC V Architecture knowledge
  • Gate Level Simulation flow bring up and experience (GLS)
  • Knowledge of UPF would be an advantage

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

Design Verification (Sub-system &/or SoC)

Design Engineer / Lead

Santa Clara, California or Bangalore, India

Job Requirements [Lead Design Engineer]:

  • 12+ years of relevant experience
  • Ability to architect a sub-system or a group of sub-systems
  • Strong background in digital design/verification/timing concepts in order to analyze trade-offs between feature set, area, performance, power, software complexity, schedule, and resourcing
  • Hands-on experience in:
  • Modem design (Lower/ Upper Phy/ MAC), or
  • Integrating Processor sub-systems and Coherent Mesh Networks, or
  • Integrating High Speed Interfaces (DDR, PCIe, CXL, Ethernet, eCPRI, JESD, USB etc)
  • Prior background in SoC or Chipset architecture is a strong plus
  • Strong digital design background
  • uArchitecture, RTL development strength – control path and datapath RTL development
  • Experience with RTL integration – ability to stitch together multiple blocks into sub-system
  • Experience in defining testplans, feature coverage, and driving verification closure
  • Must have thorough knowledge of Lint and CDC concepts
  • Must have strong understanding of design constraints and timing closure concepts
  • Exposure to wireless radio technologies (Eg: 5G/4G) and design experience of signal processing blocks is a plus
  • Must have working knowledge of CHI/AXI/AHB/APB protocols
  • Exposure to Network on Chip Interconnects is a plus
  • Experience with logic synthesis, Logic Equivalence Checks, DFT is a plus
  • Should be capable of leading a dynamic team of engineers, drive project goals with quality, schedule milestones, and have milestones adherence

Job Requirements [Design Engineer]:

  • 5+ years of relevant experience
  • Strong digital design background
  • uArchitecture, RTL development strength – control path and datapath RTL development
  • Experience with RTL integration – ability to stitch together multiple blocks into sub-system
  • Must have thorough knowledge of Lint and CDC concepts
  • Experience in defining testplans, feature coverage, and code coverage analysis
  • Strong understanding of design constraints, and timing closure concepts
  • Must have working knowledge of AXI/AHB/APB protocols
  • Experience with ARM processors/CMN/PCIe/CCIX/CXL/Ethernet/USB/eCPRI/JESD protocols is a plus
  • Exposure to Network on Chip Interconnects is a plus

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

Design Engineer / Lead

Physical Design Engineer / STA Lead

Bangalore, India

Role Summary and Responsibilities

  • Expected to work on Block/sub-system level PD 
  • PD activities including floorplanning, abstract view generation, PNR, STA, EM, IR DROP, DRCs, & schematic to layout verification
  • Work in collaboration with design team to address design challenges
  • Continous search for improvement in RTL2GDS flow to improve PPA
  • Troubleshoot a wide variety of issues, including but not limited to difficult design issues and applied proactive intervention
  • Responsible for all aspects of physical design and implementation of complex 5G/AI SOC

Role Summary and Responsibilities [STA Lead Role]:

  • Expected to work on Subsystem Level STA and support Fullchip STA
  • Own and Drive complete subsystem Timing Closure and Signoff
  • Support on Fullchip Timing Closure
  • Support and develop on existing Timing Closure and Signoff Methodology
  • Work with Front end team and create Block level and Subsystem level Constraints

Job Requirements:

  • BE/BTECH/MTECH with strong experiencein Physical Design
  • Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies.
  • Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure
  • Expertise on high frequency design methodologies
  • Good knowledge and experience in Block-level and Sub-system Floor-planning and Physical verification
  • Experience with tools like Innovus/ICC2, Tempus/Primetime/etc used in the RTL2GDSII implementation
  • Strong knowledge and experience in standard place and route flows (Innovus/Cadence flows preferred)
  • Well versed with timing constraints, STA, and timing closure
  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools
  • Ability to multi-task and flexibility to work in a start-up environment
  • Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred

Job Requirements [STA Lead Role]:

  • BE/BTECH/MTECH with strong experiencein Physical Design
  • Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies.
  • Hands-on experience on SOC & Block Level timing signoff with 4+ tape outs.
  • Strong knowledge on constraints development and validation. 
  • Strong understanding of margins/derates.
  • Good Experience in Multimode Multi corner signoff closure.
  • Strong Knowledge on IO Budgeting for blocks and creating Top-level and Block-level Clock Tree Targets.
  • Should be able to create both clock and data timing ECOs. Manual and tool based flows.
  • Experience on Cadence tools (Tempus/TSO) will be an added advantage.
  • Strong TCL Scripting skills are required.

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

Physical Design Engineer / STA Lead​

5G ASIC Designer

Santa Clara or San Diego, California

Role Summary and Responsibilities

  • Design and develop high quality functional firmware
  • Translate product requirements to FW functional requirements
  • Write detailed FW architecture specification covering functional, performance and KPI aspects
  • Develop high level design, low-level design specification
  • Design FW system to handle critical timing/synchronization to meet real-time needs of wireless protocols
  • Closely work with HW architects and system engineers to design HW-SW functional split and interfaces
  • Active part in Customer solution design
  • Functional troubleshooting at product level both in the lab and field
  • Perform effective SW/FW configuration management and release management
  • Support field performance activities and radio conformance tests

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

5G ASIC Designer

Firmware Engineering

Santa Clara or San Diego, California

Role Summary and Responsibilities

  • Have the experience on developing FW at embedded processor (e.g. ARM, RISC-V, etc)
  • Hands on experience in developing the PHY L1 layer for the communication standard (4G/5G/WLAN)
  • Have the professional knowledge/experience on C language
  • Hands on experience in FW architecture design including API definition
  • Familiar with the wireless communications standard (4G/5G/WLAN)
  • Familiar with the debugging tools (e.g. ICE, T32)
  • Ability to communicate effectively across all internal groups

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

Firmware Engineering

5G PHY Control Firmware

Santa Clara, California or Bangalore, India

Role Summary and Responsibilities

  • Design and develop high quality functional firmware
  • Translate product requirements to FW functional requirements
  • Write detailed FW architecture specification covering functional, performance and KPI aspects
  • Develop high level design, low-level design specification
  • Design FW system to handle critical timing/synchronization to meet real-time needs of wireless protocols
  • Closely work with HW architects and system engineers to design HW-SW functional split and interfaces
  • Active part in Customer solution design
  • Functional troubleshooting at product level both in the lab and field
  • Perform effective SW/FW configuration management and release management
  • Support field performance activities and radio conformance tests

Job Requirements

  • Strong knowledge of any of the wireless technologies (4G, 5G, WLAN technologies (802.11a/b/g/n/ac/ax))
  • Strong background in Wireless communication and signal processing
  • Deep understanding of embedded software engineering principles, and core computer science fundamentals
  • RTOS, C and C++, compilers, build and source code control tools;
  • Very strong coding & debugging skills in C is must
  • Proficiency debugging embedded software systems
  • Education & experience:B.Tech Degree in Electronics & Communication, Telecom System Engineering or Computer Science. MS/M.Tech Degree highly desirable
  • 2-12 years’ experience Wireless PHY, PHY control Firmware design and development

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

5G PHY Control Firmware

Digital Signal Processing (Micro-Kernel) Engineer

Santa Clara or San Diego, California

Role Summary and Responsibilities

  • Familiar with the fixed point arithmetic (e.g. Q-format, rounding, saturation, etc)
  • Have the experience on implementing DSP algorithm at DSP processor with C (e.g. TI54x, TI6x or Tensilica, etc)
  • Have the experience on implementing/optimizing DSP algorithm at DSP processor with asm / C
  • Familiar with pipelined processor (e.g. stall, RAW, WAR, WAW hazards, forwarding, etc)
  • Have the professional knowledge/experience on C language
  • Have the basic understanding on asm language
  • Have a good knowledge on Digital Signal Processing (e.g. Nyquist Sampling Theorem, LTI, Digital filter, Fourier transform, Z-transform, DFT/FFT, etc)

Accessibility:

EdgeQ is an Equal Employment Opportunity (EEO) employer and welcomes qualified applicants from around the world, regardless of their ethnicity, gender, religion, nationality, age, disability, or other legally protected status.

Digital Signal Processing (Micro-Kernel) Engineer